In using metal-oxide-semiconductor (MOS) structures for switching operations involving power supplies and AC adapters, it is desirable to reduce the gate-to-drain capacitance in order to reduce switching time and power loss.
Reduction of capacitance across gate and drain may be achieved by several methods, including: reducing the ratio of the gate width to the width of the channel region; decreasing the gate area; increasing the thickness of the gate insulation film; increasing the thickness of a part of the insulation film; and disposing an impurity diffusion layer whose conductivity type is different from that of the substrate, on a portion of the surface of the semiconductor substrate away from the channel region.
FIG. 2 shows a cross-section of a conventional MOS structure for reducing the gate-to-drain capacitance. In this embodiment incorporating a reduced gate area, p-type channel regions (2) are formed on the surface of an n-type silicon substrate (1); p.sup.+ -type regions (3), laterally interposed between regions (2), are formed on the surface of substrate (1); and n.sup.+ source regions (4) are formed on the surface portions of regions (2). Additionally, lateral spacing between the channel regions (2) is reduced.
In the embodiment of FIG. 2, gate electrodes (6) made of polycrystal silicon film are disposed on gate oxide films (5), which layer is in turn disposed on portions of the channel regions (2) located between the source regions (4) and the n-type substrate (1). The gate electrodes (6), via gate oxide films (5), are disposed also on portions of the n-type substrate between the channel regions (2). An Al--Si source electrode (7) contacts the p.sup.+ region (3) and the n.sup.+ source region (4). Additionally, the source electrode (7) is insulated by PSG films (8) from the channel regions (2) and the n-type substrate (1).
The embodiment of FIG. 2 has an operational problem. When the gate electrode (6) area is reduced in order to decrease the gate-to-drain capacitance, on-resistance of the device increases.
FIG. 3 illustrates another conventional MOS structure for reducing the gate-to-drain capacitance. In this embodiment, which has a structure similar to FIG. 2, the gate-oxide-film (5) thickness is increased while lateral spacing between the channel regions (2) is not reduced.
This embodiment also has an operational problem. Increase in the thickness of the gate-oxide film (5) results in changes of the threshold voltage, V.sub.th, and mutual conductance, g.sub.fs. Consequently, when the applied voltage is zero, the gate-to-drain capacitance is initially reduced. However, since the gate-to-drain capacitance is determined by the capacitance of the depletion layer generated in the substrate (1), as the applied voltage increases the gate-to-drain capacitance similarly increases. The net effect is that the gate-to-drain capacitance remains unchanged, as if the gate-oxide-film thickness had not been increased.
FIG. 4 illustrates another conventional MOS structure for reducing the gate-to-drain capacitance. In this embodiment, region (51) of the gate oxide film (5) is thicker than the rest of the oxide film (5). As in the structure of FIG. 3, the structure of FIG. 4 cannot effectuate reduced gate-to-drain capacitance.
FIG. 5 illustrates yet another conventional MOS structure for reducing the gate-to-drain capacitance. In this embodiment, p-type diffusion regions (9) are formed underneath the gate electrodes (6) on the surface portion of the n substrate (1). Capacitance between the gate and the drain in the impurity diffusion region is negligible. Consequently, capacitance of the structure is decreased due to reduction of capacitance between the gate and the drain. However, due to reduced area of the n-type substrate (1) interposed between the channel regions (2), junction-FET effect occurs. This phenomenon results in a problem of increased on-resistance, R.sub.DS (on)